The invention relates to the design and manufacture of integrated circuits, and more particularly, to techniques, systems, and methods for implementing metal-fill on an integrated circuit.
In recent years, in integrated circuit (IC) manufacturing, chemical-mechanical polishing (CMP) has emerged as an important technique for planarizing dielectrics because of its effectiveness in reducing local step height and achieving a measure of global planarization not normally possible with spin-on and resist etch back techniques. However, CMP processes have been hampered by layout pattern dependent variation in the inter-level dielectric (ILD) thickness which can reduce yield and impact circuit performance.
Metal-fill patterning is a common approach for reducing layout pattern dependent dielectric thickness variation. Metal-fill patterning is the process of filling large open areas on each metal layer with a metal pattern to compensate for pattern-driven variations. The manufacturer of the chip normally specifies a minimum and maximum range of metal that should be present at each portion of the die. If there is an insufficient amount of metal at a particular portion on the chip, then metal-fill is used to increase the proportion of metal in that portion. However, too much metal may cause dishing to occur. Therefore, the metal-fill process should not cause the die to exceed any specified maximum range of metal for the chip.
Even after the IC design has been completed, it is possible that additional engineering changes may be implemented at a later point in time. These additional changes may be implemented, for example, to correct an existing problem, to improve performance, or to add new functionality to the device. The process of implementing an engineering change after a device has been manufactured is often called the Engineering Change Order (ECO) process.
If the IC design does not include any dummy metal fill geometries, then the ECO could complete without having any impact on areas of the device that were not explicitly affected by the changes (e.g., in connectivity) required by the ECO. However, the ECO process is much more complicated for designs that include dummy metal fill geometries to control the effects of on-chip variation (OCV), such as IC designs for processes that use CMP.
One approach for implementing an Engineering Change Order (ECO) after a device has been manufactured is to delete dummy metal fill geometries that were added to the original design. This makes room for changes in the layout that might be required by the ECO process. By removing the dummy metal fill, the placement and routing operations have sufficient free space to be able to complete without causing shorts or design rule check (DRC) violations.
One significant problem with this approach is that the process of first removing the original dummy metal fill geometries, then implementing the ECO, and then finally inserting new dummy metal fill can lead to different timing characteristics in areas of the device that were not affected by the ECO itself. This could cause additional iterations in the ECO process to repair errors caused by the initial ECO changes.
Disclosed is an improved method and system for implementing metal fill for an integrated circuit design. In some embodiments, when an engineering change order is implemented, the existing dummy metal fill geometries are initially ignored when modifying the layout, even if this results in shorts and/or other DRC violations. Once the ECO changes have been implemented, those violations caused by interaction between the changes and the metal fill are repaired afterwards.
Further details of aspects, objects, and advantages of the invention are described below in the detailed description, drawings, and claims. Both the foregoing general description and the following detailed description are exemplary and explanatory, and are not intended to be limiting as to the scope of the invention.